The present invention relates to a multilayer chip fabricated with a variety of electronic parts such as capacitor, varistor, Negative Temperature Characteristic (NTC) thermistor, Resistor Capacitor (RC) coupled element and the like, and more particularly to a low inductance multilayer chip having a characteristic of stabile operations at high frequency by offsetting inductance with an improved internal pattern of a multilayer chip.
Recently, high frequency has been utilized for operations of electronic goods like personal portable communication devices, personal computer system, etc., so that there has also been a demand on electronic parts to be embedded in the electronic goods that can operate stably at high frequency.
The exemplary electronic parts as such are passive elements including resistor, capacitor, inductor and so on. The passive elements have generally been produced in a single element configuration, but they have also been produced in a composite element by coupling more than two passive elements to improve packaging efficiency and reduce noise among elements.
However, even if the electronic parts thus constructed have a characteristic of stable operations at a low frequency, they show unstable operations at a high frequency so that they are disadvantageous to be applied to electronic devices using a high operational frequency.
For instance, capacitor shows a stable, unique operational characteristic at a low frequency, but an increase in equivalent inductance component at a high frequency and a concomitant occurrence of parasitic oscillations or a corresponding increase in impedance to drop speed in response.
In other words, a multilayer chip capacitor, as shown in FIG. 1, includes layers having internal electrodes respectively connected to positive and negative external electrodes. As a result, current flows from the positive electrode through dielectric layers to the negative electrode, generating self-inductance to disturb the flow of current and, what""s worse, drastically increasing it at a high frequency.
In addition, a RC coupled element, as shown in FIG. 2, is generally made in a repeated arrangement of RC circuits on a chip. If a frequency-impedance characteristic of the RC coupled element as such is measured with a network analyzer, there is an increase in impedance due to an increased equivalent inductance component caused by a capacitor when operational frequency gets over hundreds of MHz and, accordingly, a drop in the response speed of the RC coupled element.
It is an object of the present invention to solve the aforementioned problems and provide a low inductance multilayer chip having a characteristic of stable operations at high frequency with an improvement in an internal pattern of the multilayer chip to offset inductance by making in reverse the current directions flow through internal electrodes of neighboring layers and a method for fabricating the same.
It is another object of the present invention to provide a low inductance multilayer chip having a characteristic of stable operations at high frequency by employment of resistance in through holes of the chip and formation of capacitor layers in which current can flow in the reverse directions at neighboring layers and a method for fabricating the same.
It is a further anther object of the present invention to provide a low inductance multilayer chip having a characteristic of stable operations at high frequency by formation of capacitor layers in which current can flow in the reverse directions at neighboring layers and stacking of resistor layer and the capacitor layers, and a method for fabricating the same.
It is a still another object of the present invention to provide a multilayer chip that can conveniently adjust resistance value by printing resistive paste onto the surface of green sheets for formation of resistor layers and stacking of capacitor layers and the resistor layers, and a method for fabricating the same.
In order to accomplish the aforementioned objects of the present invention, there is provided a low inductance multilayer chip of the present invention, the chip having a plurality of stacked layers formed internal electrodes thereon wherein the internal electrodes are electrically connected to reverse the current directions flowing in the internal electrodes of neighboring layers.
In addition, in order to accomplish the aforementioned objects of the present invention, there is provided another low inductance multilayer chip, the chip comprising: a stacked structure having a plurality of green sheets with at least more than one through hole; internal electrodes formed on the green sheet; external electrodes formed at both ends of the stacked structure to be electrically connected with a predetermined internal electrode; and conductive material formed in the through holes to reverse the current directions flowing in the internal electrode of the neighboring green sheets by electrically connecting the internal electrodes of the predetermined green sheets.
Besides, in order to accomplish the aforementioned objects of the present invention, there is provided another low inductance multilayer chip, the chip having a plurality of stacked layers formed internal electrodes thereon wherein the internal electrodes are electrically connected by resistive material to reverse the current directions flowing in the internal electrodes of neighboring layers.
Furthermore, in order to accomplish the aforementioned objects of the present invention, there is provided another low inductance multilayer chip, the chip comprising: a stacked structure of a plurality of green sheets with at least more than one through holes; internal electrodes formed in the green sheets; external electrodes formed at both ends of the stacked structure to be electrically connected with a predetermined internal electrode; and conductive material formed in the through holes to reverse the current directions flowing in the internal electrode of the neighboring green sheets by electrically connecting the internal electrodes of the predetermined green sheets.
Also, in order to accomplish the aforementioned objects of the present invention, there is provided another low inductance multilayer chip, the chip comprising resistor layers; and capacitor layers wherein the internal electrodes of the predetermined layers are electrically connected to reverse current directions flowing in the internal electrodes of neighboring layers.
Additionally, in order to accomplish the aforementioned objects of the present invention, there is provided another multilayer chip, the chip comprising: capacitor layers; resistor layers constructed with at least more than one green sheet, the surface of which is printed by resistive material; and external electrodes formed at both ends of the stacked structure constructed with the capacitor layers and resistor layers for electrical connection.
On the other hand, in order to accomplish the aforementioned objects of the present invention, there is provided a method for fabricating a low inductance multilayer chip, the method comprising the steps of: manufacturing green sheets; forming through holes in the green sheets; forming internal electrodes on the surface of the green sheets and in the through holes; stacking the green sheets to reverse the current directions flowing in the internal electrodes of the adjacent green sheets by electrically connecting the internal electrodes formed on the surface of the predetermined green sheets through those formed in the through holes; compressing the stacked green sheets; thermally plasticizing the compressed stacked structure; and forming external electrodes at both ends of the stacked structure for electrical connection with the predetermined internal electrodes.
Also, in order to accomplish the aforementioned objects of the present invention, there is provided another method for fabricating a low inductance multilayer chip, the method comprising the steps of: manufacturing green sheets; forming through holes in the green sheets; forming resistive material in the through holes; forming internal electrodes on the green sheets; stacking the green sheets to reverse the current directions flowing in the internal electrodes of neighboring green sheets by electrically connecting the internal electrodes of the predetermined green sheets through the resistive material of the through holes; compressing the stacked green sheets; thermally plasticizing the compressed stacked structure; and forming external electrodes at both ends of the stacked structure for electrical connection of the predetermined internal electrodes.
In addition, in order to accomplish the aforementioned objects of the present invention, there is provided a method for fabricating a low inductance multilayer chip, the method comprising the steps of: manufacturing resistor layers; manufacturing capacitor layers with internal electrodes being electrically connected to reverse the current directions flowing in the internal electrodes of adjacent layers; stacking and compressing the resistor layers and capacitor layers; thermally plasticizing the compressed stacked structure; and forming external electrodes at both ends of the stacked structure for electrical connection with the resistor layers and capacitor layers.
Furthermore, in order to accomplish the aforementioned objects of the present invention, there is provided a method for fabricating a multilayer chip, the method comprising the steps of: manufacturing resistor layers by forming resistive material on the surface of green sheets; manufacturing capacitor layers; stacking and compressing the resistor layers and capacitor layers; thermally plasticizing the compressed stacked structure; and forming external electrodes at both ends of the stacked structure for electrical connection with the resistor and capacitor layers.